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1 motorola tmos power mosfet transistor device data
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? ? nchannel enhancementmode silicon gate this advanced high voltage tmos efet is designed to withstand high energy in the avalanche mode and switch efficiently. this new high energy device also offers a draintosource diode with fast recovery time. designed for high voltage, high speed switching applications such as power supplies, pwm motor controls and other inductive loads, the avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. ? 2500 v rms isolated isotop package ? avalanche energy specified ? sourcetodrain diode recovery time comparable to a discrete fast recovery diode ? diode is characterized for use in bridge circuits ? very low internal parasitic inductance ? i dss and v ds(on) specified at elevated temperature ? u. l. recognized, file #e69369 maximum ratings (t c = 25 c unless otherwise noted) rating symbol value unit drainsource voltage v dss 500 vdc draingate voltage (r gs = 1.0 m w ) v dgr 500 vdc gatesource voltage e continuous gatesource voltage e nonrepetitive (t p 10 ms) v gs v gsm 20 40 vdc vpk drain current e continuous drain current e continuous @ 100 c drain current e single pulse (t p 10 m s) i d i d i dm 53 33 210 adc total power dissipation derate above 25 c p d 460 3.70 watts w/ c operating and storage temperature range t j , t stg 40 to 150 c single pulse draintosource avalanche energy (v dd = 25 vdc, v gs = 10 vdc, i l = 53 apk, l = 0.29 mh, r g =25 w ) e as 400 mj rms isolation voltage v iso 2500 vac thermal resistance e junction to case thermal resistance e junction to ambient r q jc r q ja 0.28 62.5 c/w maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c designer's data for aworst caseo conditions e the designer's data sheet permits the design of most circuits entirely from the information presented. soa limit curves e representing boundaries on device characteristics e are given to facilitate aworst caseo design. efet is a trademark of motorola, inc. tmos is a registered trademark of motorola, inc. isotop is a trademark of sgsthomson microelectronics. preferred devices are motorola recommended choices for future use and best overall value. rev 2 order this document by mTE53N50E/d semiconductor technical data tmos power fet 53 amperes 500 volts r ds(on) = 0.080 ohm motorola preferred device d s g ? sot227b 1 2 3 4 1. source 2. gate 3. drain 4. source 2 ? motorola, inc. 1996
2 motorola tmos power mosfet transistor device data electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drainsource breakdown voltage (v gs = 0 vdc, i d = 250 m adc) temperature coefficient (positive) v (br)dss 500 e 560 550 e e vdc mv/ c zero gate voltage drain current (v ds = 500 vdc, v gs = 0 vdc) (v ds = 500 vdc, v gs = 0 vdc, t j = 125 c) i dss e e e e 10 100 m adc gatebody leakage current (v gs = 20 vdc, v ds = 0) i gss e e 200 nadc on characteristics (1) gate threshold voltage (v ds = v gs , i d = 250 m adc) threshold temperature coefficient (negative) v gs(th) 2.0 e 3.2 e 4.0 e vdc mv/ c static drainsource onresistance (v gs = 10 vdc, i d = 26.5 adc) r ds(on) e 63 80 mohm drainsource onvoltage (v gs = vdc) (i d = 53 adc) (i d = 26.5 adc, t j = 125 c) v ds(on) e e e e 4.8 4.3 vdc forward transconductance (v ds = 15 vdc, i d = 26.5 adc) g fs 25 45 e mhos dynamic characteristics input capacitance (v 25 vdc v 0 vdc c iss e 14400 e pf output capacitance (v ds = 25 vdc, v gs = 0 vdc, f = 1.0 mhz ) c oss e 1560 e reverse transfer capacitance f = 1 . 0 mhz) c rss e 240 e switching characteristics (2) turnon delay time (v 250 vd i 53 ad t d(on) e 67 e ns rise time (v dd = 250 vdc, i d = 53 adc, v gs =10vdc t r e 322 e turnoff delay time v gs = 10 vd c, r g = 4.7 w ) t d(off) e 362 e fall time g ) t f e 310 e gate charge (v 400 vd i 53 ad q t e 474 700 nc (v ds = 400 vdc, i d = 53 adc, q 1 e 86 e ( ds , d , v gs = 10 vdc) q 2 e 206 e q 3 e 148 e sourcedrain diode characteristics forward onvoltage (1) (i s = 53 adc, v gs = 0 vdc) (i s = 53 adc, v gs = 0 vdc, t j = 125 c) v sd e e 0.95 0.90 1.3 e vdc reverse recovery time (i 53 ad v 0 vd t rr e 720 e ns (i s = 53 adc, v gs = 0 vdc, t a e 460 e ( s , gs , di s /dt = 100 a/ m s) t b e 260 e reverse recovery stored charge q rr e 15 e m c internal package inductance internal drain inductance (measured from contact screw on tab to center of die) (measured from the drain lead 0.25 from package to center of die) l d e e 3.5 5.0 e e nh internal source inductance (measured from the source lead 0.25 from package to center of die) l s e 5.0 e nh (1) pulse test: pulse width 300 m s, duty cycle 2%. (2) switching characteristics are independent of operating junction temperature.
3 motorola tmos power mosfet transistor device data typical electrical characteristics r ds(on) , draintosource resistance (normalized) r ds(on) , draintosource resistance (ohms) 0 v ds , draintosource voltage (volts) figure 1. onregion characteristics i d , drain current (amps) i d , drain current (amps) v gs , gatetosource voltage (volts) figure 2. transfer characteristics i d , drain current (amps) figure 3. onresistance versus drain current and temperature i d , drain current (amps) figure 4. onresistance versus drain current and gate voltage t j , junction temperature ( c) figure 5. onresistance variation with temperature v ds , draintosource voltage (volts) figure 6. draintosource leakage current versus voltage t j = 25 c v gs = 10 v v gs = 10 v i d = 26.5 a 7 v 6 v 50 0 50 100 150 120 80 40 20 0 9 7 6 4 2 120 80 60 0 6 5 2 100 40 60 40 20 0 80 120 0 100 300 200 400 500 5 v 4 v 125 135 8 v 20 34 v ds 10 v 100 c 25 c t j = 55 c 0.16 0.12 0.08 0.04 0 0 40 60 80 100 120 t j = 100 c 25 c 55 c 0.085 0.08 0.075 0.07 0.065 0.06 v gs = 10 v t j = 25 c v gs = 10 v 15 v r ds(on) , draintosource resistance (ohms) 25 25 75 2.5 2 1.5 1 0.5 0 i dss , leakage (na) 100000 10000 1000 100 10 1 v gs = 0 v t j = 125 c 100 c 25 c 100 60 8 20 100
4 motorola tmos power mosfet transistor device data power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( d t) are deter- mined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculat- ing rise and fall because draingate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resis- tive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turnon and turnoff delay times, gate current is not constant. the simplest calculation uses appropriate val- ues from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the offstate condition when cal- culating t d(on) and is read at a voltage corresponding to the onstate when calculating t d(off) . at high switching speeds, parasitic circuit elements com- plicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a func- tion of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to mea- sure and, consequently, is not specified. the resistive switching time variation versus gate resis- tance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely op- erated into an inductive load; however, snubbing reduces switching losses. gatetosource or draintosource voltage (volts) c, capacitance (pf) figure 7. capacitance variation 60000 0 v gs v ds 50 510152025 10 50000 40000 30000 20000 10000 v gs = 0 v v ds = 0 v t j = 25 c c rss c oss c iss c iss c rss draintosource voltage (volts) c, capacitance (pf) figure 7b. high voltage capacitance variation 100000 10 100 1000 10 10000 1000 100 v gs = 0 v t j = 25 c c rss c oss c iss
5 motorola tmos power mosfet transistor device data q g , total gate charge (nc) 400 figure 8. gatetosource and draintosource voltage versus total charge r g , gate resistance (ohms) 1 10 100 10000 10 t, time (ns) v dd = 250 v i d = 53 a v gs = 10 v t j = 25 c t r t f t d(off) t d(on) figure 9. resistive switching time variation versus gate resistance v gs , gatetosource voltage (volts) 0 10 8 4 0 12 500 i d = 53 a t j = 25 c 100 200 300 100 v ds , draintosource voltage (volts) 6 2 qt q1 q2 q3 v gs v ds 420 350 280 210 140 70 0 1000 safe operating area the forward biased safe operating area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is for- ward biased. curves are based upon maximum peak junc- tion temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, atransient thermal resistancegeneral data and its use.o switching between the offstate and the onstate may tra- verse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded and the transition time (t r ,t f ) do not exceed 10 m s. in addition the total power aver- aged over a complete switching cycle must not exceed (t j(max) t c )/(r q jc ). a power mosfet designated efet can be safely used in switching circuits with unclamped inductive loads. for reli- able operation, the stored energy from circuit inductance dis- sipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a con- stant. the energy rating decreases nonlinearly with an in- crease of peak current in avalanche and peak junction temperature. v sd , sourcetodrain voltage (volts) figure 10. diode forward voltage versus current i s , source current (amps) v gs = 0 v t j = 25 c 60 50 40 30 20 10 0 1.1 1 0.9 0.8 0.7 0.6 0.5
6 motorola tmos power mosfet transistor device data safe operating area figure 11. maximum rated forward biased safe operating area di/dt t rr t a t p i s 0.25 i s time i s t b figure 12. maximum avalanche energy versus starting junction temperature 0.1 1 1000 v ds , draintosource voltage (volts) figure 13. thermal response 1000 i d , drain current (amps) r ds(on) limit thermal limit package limit 0.1 10 v gs = 20 v single pulse t c = 25 c 100 t, time (s) figure 14. diode reverse recovery waveform r(t), effective transient thermal resistance (normalized) 1 0.0001 d = 0.5 0.2 0.1 0.05 0.02 single pulse 1 ms 10 ms dc 10 0.1 1.0e05 1.0e04 1.0e03 1.0e02 1.0e01 1.0e+00 1.0e+01 100 m s 400 350 300 250 200 150 100 50 0 25 50 75 100 125 150 i d = 53 a t j , starting junction temperature ( c) e as , single pulse draintosource avalanche energy (mj) 0.01 0.001 0.01 1 100 chip junction ambient 0.0318 f 0.1239 f 0.9536 f 0.0315 w 0.1856 w 0.0629 w
7 motorola tmos power mosfet transistor device data package dimensions sot227b notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeters. dim a min max min max inches 31.50 31.70 1.240 1.248 millimeters b 7.80 8.20 0.307 0.322 c 4.10 4.30 0.161 0.169 d 14.90 15.10 0.586 0.590 e 30.10 30.30 1.185 1.193 f 38.00 38.20 1.496 1.503 g 4.00 0.157 h 11.80 12.20 0.464 0.480 l 8.90 9.10 0.350 0.358 m 12.60 12.80 0.496 0.503 n 25.20 25.40 0.992 1.000 p 1.95 2.05 0.076 0.080 q 4.10 0.157 r 0.75 0.85 0.030 0.033 s 5.50 0.217 style 1: pin 1. source 2. gate 3. drain 4. source 2 q g c b a 12 3 4 d e f m n r l h p s recommended screw torque: 1.3 0.2 nm maximum screw torque: 1.5 nm
8 motorola tmos power mosfet transistor device data motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, 6f seibubutsuryucenter, p.o. box 20912; phoenix, arizona 85036. 18004412447 or 6023035454 3142 tatsumi kotoku, tokyo 135, japan. 038135218315 mfax : rmfax0@email.sps.mot.com touchtone 6 022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok r oad, tai po, n.t., hong kong. 85226629298 mTE53N50E/d
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